A receiver of a high speed serial data link may be subject to noise caused by impedance discontinuities caused by connectors, amongst other things. Such noise may limit the data rate of the link. As data rates continue to increase, the impedance discontinuities may cause reflections that occur many unit intervals after an initial transition occurs (e.g. when a pulse is transmitted). These reflections may result in significant inter-symbol interference to later transmitted bits, which interference may be difficult to compensate for at the receiver.
The prior art includes techniques to deal with interference. For example, decision feedback equalization (DFE) is one current receiver technique for removing such inter-symbol interference. However, DFE typically requires a significant amount of integrated circuit die area and power. Current DFE techniques require one tap for each unit interval of time to be compensated. Hundreds of taps may be required to equalize a 10 Gbps link having 3.5 ns of delay between the transmitter and receiver. In addition, current DFE techniques result in a significant latency hit because a bit must be equalized before its value is determined. Moreover, conventional equalization techniques at the transmitter side of the data link typically make use of the first few bits after the transmitted bit for equalization. That is, transmitter equalization typically cannot handle impedance discontinuities that cause reflections many unit intervals after a bit transition occurs. Hence, there is a need in the art for improved techniques to deal with noise, inter-symbol interference, reflections, and other problems encountered when using high speed serial data links.